MN-Core ASIC Front End Design Engineer

Job Description

We are looking for an engineer to design the ASIC, which is the heart of PFN's computational infrastructure.

PFN's various R&D and businesses are supported by a huge amount of computation centered on machine learning and simulation. The heart of the computational infrastructure is the accelerator, and PFN develops and utilizes the accelerator MN-Core ™ based on our own principle and its successor, MN-Core 2 (tentative name under development). As of 2022, MN-Core is the number one in the world on the Green500 List, which competes for the power saving performance of supercomputers, and is overwhelming by more than 15% compared to the second and lower companies using more advanced semiconductor processes. I'm making a difference. This shows the design advantage of MN-Core.

In the future, in order to strengthen the development of the MN-Core series, we are looking for an ASIC front-end engineer who will be in charge of continuous research and development. We are waiting for applications from those who are enthusiastic about the global battle in architecture and semiconductor design.

Responsibilities

In this job, you will be responsible for the following ASIC front-end design tasks from MN-Core architecture design to RTL coding & verification, and machine bring-up.

• R&D of MN-Core Architecture
• ASIC / Functional Block Specification
• RTL Coding
• Logic Verification
• Synthesis/STA
• Support back-end vendor
• bring-up/debug

Qualifications

Strong motivation for the relevant field

• Those who are excited about "chip development aiming for the best in the world"
• Those who can adapt to fast-growing fields and absorb knowledge enthusiastically
• Interest in a wide range of technical fields

High ASIC design skills

• Over 5 years experience on ASIC design
• Strong leadership

In addition, two or more of the following experience and skills.

• Architecture design experience for CPU, Accelerator etc…
• RTL(Verilog HDL/SystemVerilog/VHDL) coding skill
• Experience of logic verification and developing its environment with SystemVerilog or SystemC

Preferred Requirements

• over 8 years experience of ASIC design
• Deep knowledge of computer architecture
• IP knowledge (PCIe, DDR etc…)
• experience of logic synthesis and STA
• Knowledge of computational kernel on deep learning
• Coding experience of deep learning program
• skill of assembler coding
• experience of random verification and developing its environment
• experience of board development
• experience of compiler, computation library, driver development
• experience of development with version control systems (Git, GitHub, GitLab, Subversion etc…)

Attractive Points

• Be part of creating a new world
• Engage in the development of the next generation of MN-Core, which has won first place in the Green500 three times.
• Gain knowledge and experience in ASIC development targeting deep learning, which is currently the focus of much attention
• Work on ASIC development with world-class performance
• Work with highly skilled team members
  Work closely with SW engineers and discuss development with them.

Contents in a Resume

• The format of your resume does not need to follow any particular one. To help us understand as much as possible about you, please write about projects you have participated in, part-time jobs/internships, papers you have written, implementations you have published, etc.
• Please include links to your own technical blogs, GitHub repositories, and papers, if any.

About the Company

Preferred Networks (PFN) was established in March 2014 with the goal to develop practical, real-world applications of deep learning, robotics and other advanced technologies. PFN’s business domains include transportation, manufacturing, life sciences, robots, plant optimization, materials discovery, education and entertainment. In 2015, PFN developed Chainer™, the open-source deep learning framework. PFN’s MN-3 supercomputer, which is equipped with the MN-Core™ deep learning processor, topped the Green500 list three times in 2020 and 2021.

Benefits

Employment Type

• Full-time regular employment
• Probation period: 3 months (under the same condition as regular employment)

Location

• Otemachi Bldg., 1-6-1 Otemachi, Chiyoda-ku, Tokyo
• Remote work system available

Work Schedule

• Five-day workweek (Saturdays and Sundays off), public holidays, New Year’s holiday
• Discretionary-work (deemed work hours: 8 hours) or Flex-time system
• Annual paid leave based on company regulations

Compensation

• Experience, performance, skills, contribution are taken into consideration.
• Periodic assessment (2 times a year)
• In addition to basic salary, bonuses are paid based on company’s performance and individual contribution. (Twice a year: Apr/Oct)
• Commutation expenses

Welfare

• Various social insurance programs: pension insurance, health insurance, employment insurance, workers’ compensation
• Vacation: maternity leave, parental leave, congratulation or condolence leave
• Regular health checks
• Allowance for purchasing a laptop PC.
• Defined contribution pension